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The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
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HM62V16514I Series
Wide Temperature Range Version 8 M SRAM (512-kword x 16-bit)
ADE-203-1280B (Z) Rev. 1.0 Mar. 15, 2002
Description
The Hitachi HM62V16514I Series is 8-Mbit static RAM organized 524,288-word x 16-bit. HM62V16514I Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII.
Features
* * * Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 55 ns (Max) Power dissipation: Active: 6.0 mW/MHz (Typ) Standby: 1.5 W (Typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. Temperature range: -40 to +85C
* * * * *
HM62V16514I Series
Ordering Information
Type No. HM62V16514LTTI-5 HM62V16514LTTI-5SL Access time 55 ns 55 ns Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DE)
2
HM62V162514I Series
Pin Arrangement
44-pin TSOP A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13
Pin Description
Pin name A0 to A18 I/O0 to I/O15 CS WE OE LB UB VCC VSS Function Address input Data input/output Chip select Write enable Output enable Lower byte select Upper byte select Power supply Ground
3
HM62V16514I Series
Block Diagram
LSB V CC V SS
* * * * *
A5 A6 A7 A4 A3 A8 A9 A10 A11 A12 MSB A13
Row decoder
Memory matrix 2,048 x 2,048
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
LSB A15 A16 A17 A18 A0 A1 A2 A14MSB
* *
CS LB UB WE OE
Control logic
4
HM62V162514I Series
Operation Table
CS H x L L L L L L L WE x x H H H L L L H OE x x L L L x x x H UB x H L H L L H L x LB x H L L H L L H x I/O0 to I/O7 High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Note: H: V IH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to + 4.6 -0.5* to V CC + 0.3* 1.0 -55 to +125 -40 to +85
1 2
Unit V V W C C
Notes: 1. VT min: -3.0 V for pulse half-width 30 ns. 2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 2.7 0 2.2 -0.3 -40 Typ 3.0 0 -- -- -- Max 3.6 0 VCC + 0.3 0.6 85 Unit V V V V C 1 Note
1. VIL min: -3.0 V for pulse half-width 30 ns.
5
HM62V16514I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | -- -- Typ* 1 Max -- -- 1 1 Unit A A Test conditions Vin = VSS to V CC CS = VIH or OE = VIH or WE = VIL or, LB = UB =VIH , VI/O = VSS to V CC CS = VIL, Others = VIH/VIL, I I/O = 0 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS = VIL, Others = VIH/VIL Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS 0.2 V, VIH V CC - 0.2 V, VIL 0.2 V CS = VIH 0 V Vin (1) CS V CC - 0.2 V or (2) LB = UB V CC - 0.2 V, CS 0.2 V
Operating current Average operating current
I CC I CC1
-- --
-- 16
20 30
mA mA
I CC2
--
2
5
mA
Standby current Standby current
I SB I SB1*
2
-- --
0.1 0.5
0.3 25
mA A
I SB1*3 Output high voltage Output low voltage VOH VOL
-- 2.2 --
0.5 -- --
10 -- 0.4
A V V I OH = -1 mA I OL = 2 mA
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. This characteristic is guaranteed only for L version. 3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
6
HM62V162514I Series
AC Characteristics (Ta = -40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig)
VTM
R1 Dout R1 = 3070 30pF R2 R2 = 3150 VTM = 2.8 V
7
HM62V16514I Series
Read Cycle
HM62V16514I -5 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB, UB access time Chip select to output in low-Z LB, UB enable to low-z Output enable to output in low-Z Chip deselect to output in high-Z LB, UB disable to high-Z Output disable to output in high-Z Symbol t RC t AA t ACS t OE t OH t BA t CLZ t BLZ t OLZ t CHZ t BHZ t OHZ Min 55 -- -- -- 10 -- 10 5 5 0 0 0 Max -- 55 55 35 -- 55 -- -- -- 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
8
HM62V162514I Series
Write Cycle
HM62V16514I -5 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB, UB valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in High-Z Write to output in high-Z Symbol t WC t AW t CW t WP t BW t AS t WR t DW t DH t OW t OHZ t WHZ Min 55 50 50 40 50 0 0 25 0 5 0 0 Max -- -- -- -- -- -- -- -- -- -- 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 6 7 5 4 Notes
Notes: 1. t CHZ, tOHZ , t WHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS, a low WE and a low LB or a low UB. A write begins at the latest transition among CS going low, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS going high, WE going high and LB going high or UB going high. t WP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS going low to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS or WE going high to the end of write cycle.
9
HM62V16514I Series
Timing Waveform
Read Cycle
t RC Address tAA tACS CS tCLZ*2, 3 tCHZ*1, 2, 3 tBHZ*1, 2, 3 tBA LB, UB tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE tOLZ*2, 3 Dout High impedance Valid data tOH Valid address
10
HM62V162514I Series
Write Cycle (1) (WE Clock)
tWC Address Valid address tWR*7
tCW*5 CS tBW LB, UB tAW tWP*4 WE tAS*6 tDW Din tWHZ*1, 2 Valid data
tDH
tOW*2 High impedance
Dout
11
HM62V16514I Series
Write Cycle (2) (CS Clock, OE = VIH)
tWC Address Valid address tAW tAS*6 CS tBW LB, UB tCW*5 tWR*7
tWP*4 WE tDW Din Valid data tDH
High impedance Dout
12
HM62V162514I Series
Write Cycle (3) (LB, UB Clock, OE = VIH)
tWC Address Valid address tAW tCW*5 CS tAS*6 LB, UB tBW tWR*7
tWP*4 WE tDW Din Valid data tDH
High impedance Dout
13
HM62V16514I Series
Low VCC Data Retention Characteristics (Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 4 -- Max 3.6 Unit V Test conditions*3 Vin 0V (1) CS V CC - 0.2 V or (2) LB = UB V CC - 0.2 V CS 0.2 V VCC = 3.0 V, Vin 0V (1) CS V CC - 0.2 V or (2) LB = UB V CC - 0.2 V CS 0.2 V
Data retention current
I CCDR*1
--
0.5
25
A
I CCDR*2 Chip deselect to data retention time t CDR Operation recovery time tR
-- 0 t RC*
5
0.5 -- --
10 -- --
A ns ns See retention waveform
Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for L-SL version. 3. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If LB, UB controls data retention mode, LB, UB must be LB = UB V CC - 0.2 V, CS must be CS 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 5. t RC = read cycle time.
14
HM62V162514I Series
Low V CC Data Retention Timing Waveform (1) (CS Controlled)
Data retention mode tR
t CDR V CC 2.7 V
2.2 V V DR CS 0V CS VCC - 0.2 V
Low V CC Data Retention Timing Waveform (2) (LB, UB Controlled)
Data retention mode tR
t CDR V CC 2.7 V
2.2 V V DR LB, UB 0V LB, UB VCC - 0.2 V
15
HM62V16514I Series
Package Dimensions
HM62V16514LTTI Series (TTP-44DE)
As of July, 2001
18.41 18.81 Max 44 23
Unit: mm
1 *0.27 0.07 0.25 0.05
0.80 0.13 M
22 0.80
10.16
1.005 Max *0.145 0.05 0.125 0.04
11.76 0.20 0.50 0.10 0.68 0 - 5 0.13 0.05
1.20 Max
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC JEITA Mass (reference value)
TTP-44DE -- -- 0.43 g
16

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